1. Field of Invention
The present invention relates to a method for fabricating a non-volatile memory (NVM). Particularly, the present invention relates to a method for fabricating a flash memory.
2. Description of Related Art
Flash memory is a type of electrically erasable programmable read-only memory (E2 PROM). A flash memory can be programmed, read, and erased repeatedly and can retain data even if power is switched off, and therefore is widely used in personal computers and in electronic apparatuses.
A conventional flash memory uses a floating gate and a control gate both made from doped polysilicon. When the flash memory is to be programmed, the control gate and the source/drain of a selected memory cell are applied with appropriate biases. An electron flow from the source to the drain is thereby induced in the channel. The electron flow can produce hot electrons that will tunnel through the tunnel oxide layer and into the floating gate and will distribute evenly in the floating gate. A flash memory is usually programmed by the above-mentioned channel hot-electron injection (CHEI) mechanism and is usually erased by the Fowler-Nordheim tunneling mechanism. The disadvantage of the conventional flash memory is that a leakage easily occurs in the memory cell if there are weak points in the tunnel oxide layer, and the reliability of the device is thus lowered.
To solve the leakage problem of a flash memory, a charge-trapping layer is recently developed to replace the polysilicon floating gate in the conventional flash memory. The charge-trapping layer usually comprises a silicon nitride layer that is disposed between two silicon oxide layers to form an oxide/nitride/oxide (ONO) composite layer, while the memory with a nitride charge-trapping layer is known as a “nitride read-only memory (NROM)”. In a NROM, the nitride charge-trapping is able to trap electrons so that the injected hot electrons will not distribute evenly in the charge-trapping layer, but will be localized in a region of the charge-trapping layer near the drain with a Gaussian spatial distribution. Because the injected electrons are localized, the charge-trapping region is small and is less likely to locate on the weak points of the tunnel oxide layer. A leakage therefore does not easily occur in the device.
Besides, since the electrons are localized in a region of the charge-trapping layer near the drain, the NROM is capable of storing two bits in one memory-cell. This is achieved by changing the direction of the current in the channel and thus varying the generating site and the injecting region of the hot electrons. Particularly, if a higher bias is applied to the first source/drain doped region of the memory cell, hot electrons will be generated and be injected into the charge-trapping layer near the second source/drain doped region. Similarly, if a higher bias is the applied to the second source/drain doped region, hot electrons will be generated and be injected into the charge-trapping layer near the first source/drain doped region. Thus, a memory cell can be configured into one of the four states, in which each of the two ends of the charge-trapping layer may have one group of electrons with a Gaussian spatial distribution or have zero electron trapped in it.
Currently, a NROM such formed is easily affected by the process conditions. For example, when a NROM is exposed to an UV irradiation, electron-hole pairs will be created in the substrate and some of the electrons generated will diffuse into the charge-trapping layer. Since the electrons stored in the charge-trapping layer are difficult to eliminate, data errors are encountered in the NROM device.